1. Field of the Invention
The present invention relates to a recess-gate structure and a method for forming the same, and more particularly, to a recess-gate structure in which the junctions have a thickness sufficiently smaller than the thickness of a device isolation layer to prevent shorting of the junctions located at opposite lateral sides of the device isolation layer close thereto, resulting in improvement in the operational reliability of a resultant device, and a method for forming the same.
2. Description of the Related Art
As the integration density of dynamic random access memory (DRAM) cells increases, transistors are gradually decreasing in size and the length of a channel between a source and a drain of transistors is also decreasing.
Such a decrease of the channel length exacerbates the short-channel effect of transistors, lowering a threshold voltage of transistors.
One proposal put forward to prevent the lowering of the threshold voltage due to the transistor's short-channel effect is to increase the dopant density in the channel until the threshold voltage reaches a desired level.
Increasing the dopant density, however, tends to concentrate electric fields on source junctions and to aggravate the leakage of current, resulting in a deterioration in the refresh characteristics of DRAM cells.
In an attempt to solve the above problem, research is underway to develop recess-gate structures.
A representative example of conventional recess-gate structures will be explained below in detail with reference of the accompanying drawing.
FIG. 1 illustrates a conventional recess-gate structure in section.
As shown in FIG. 1, the conventional recess-gate structure comprises a silicone substrate 100 in which an active region and a device isolation region are defined using a device isolation layer 105, a plurality of gates 300 formed on the substrate 100, gate spacers 160 each formed by sequentially stacking a buffer oxide layer 151 and a nitride layer 153 in that order on the side wall of the gate 300, and junctions 180 formed in the substrate 100 at opposite lateral sides of the respective gates 300 and defining an asymmetrical structure relative to each other.
Here, the junctions 180 form storage and bit line nodes, and therefore the storage and bit line nodes define an asymmetrical structure. This asymmetrical structure is effective to prevent the concentration of the electric fields on the storage nodes as source junctions and to improve the resistance characteristics of the bit line node.
In the conventional recess-gate structure described above, the gates 300 are formed in a recess having a stepped profile consisting of a bottom plane, top plane, and vertical plane. Referring to circle C shown in FIG. 1, the bottom plane of the stepped recess extends over the storage node and part of the device isolation layer 105 to eliminate a height difference between the bottom of the gate 300 formed on the device isolation layer 105 and the top of the junction 180 formed as the storage node in part of the active region close to the device isolation layer 105.
By virtue of such a gate recess having the stepped profile, the recess-gate structure of the prior art achieves an increased channel length, thereby effectively preventing a short-channel effect of transistors without increasing the dopant density in the channel.
However, because the bottom plane of the gate recess extends over the storage node and part of the device isolation layer adjacent to the storage node to eliminate the height difference between the gate and the junction, the height of the storage node is lowered to a value B far below an original design value A. That is, the junction as the storage node is lowered in height, and so the thickness of the junction is substantially equal to the thickness of the device isolation layer. This causes a problem of shorting between the junctions formed in the active region at opposite lateral sides of the device isolation layer close thereto (See dotted arrows shown in FIG. 1).
Additionally, in the gate recess having the stepped profile, the top plane thereof is offset from the bottom plane by the height of the vertical plane of the stepped profile. Thereby, during an etching process to form the gate recess, if the gate recess is etched based on the bottom plane by a predetermined etching slope, the top plane of the gate recess inevitably counters a relatively steep etching slope, causing damage to the junction adjacent thereto. Conversely, if the gate recess is etched based on the top plane by a predetermined etching slope, it results in a relatively dull etching slope on the bottom plane of the recess. This makes it impossible to accurately etch a material, which will form a gate electrode, to a desired depth, causing the residue of the etched material to remain on the substrate. The residue is problematic because it electrically connects adjacent gates.
If metal plugs are formed on the substrate without removing the residue of the gate electrode material, the resultant gates are also electrically connected with the metal plugs, preventing the gates from functioning as ON/OFF switches for the transistors.